Verification outfit Avery Design Systems has teamed up with high-speed connectivity IP innovator CoMira Solutions to enable chiplet design using the UCIe (Universal Chiplet Interconnect Express) die-to-die interface standard.
The idea is that by combining Avery’s verification IP (VIP) and functional verification platform and CoMira’s high-speed protocol stack controller technology you will get a good method of designing and verifying multi-die systems using the UCIe standard.
For those who came in late, UCIe was announced earlier this year as a mean to provide interoperability of chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level.
The focus of the initial specification (Version 1.0) covers the UCIe Adapter and PHY including die-to-die I/O physical layer, Die-to-Die protocols, and software stack which use the PCI Express (PCIe) and Compute Express Link (CXL) industry standards in addition to a protocol-agnostic raw transfer mode.
CoMira founder and CEO of said Qasim Shami said: “Avery provides the ideal verification environment to allow pre-silicon validation for the entire chiplet system.”
“A key to success for any standard is a broad and robust ecosystem. Avery’s experience in enabling critical technology that is compliant with emerging standards accelerates timely, accurate design and verification to help meet the market requirements,” said Chris Browy, vice president sales and marketing at Avery.
