Intel’s Knight’s Hill cut down to 10nm

intel_log_reversedIntel is telling the world+dog that it talks to that its third-generation Xeon Phi, codenamed Knight’s Hill, will use 10nm technology and its second iteration of Omni-Path fabric. TechEye and ChannelEye are not in Intel’s good books again, so we have to sneak under the radar.

Intel is not talking to us any more. Sniff.

Knight’s Hill is a long way from being in the shops. We still have to see the 14nm Knight’s Landing which is not going to be in the shops until summer of 2015. This could mean that Knights Hill is likely for 2017.

Knight’s Landing will use the same Silvermont architecture that powers Intel’s Bay Trail but it will  support four threads per CPU — currently Silvermont doesn’t use hyper-threading marchitecture at all.

The reason we are interested in Knight’s Hill is that information on it is about as rare as a 1970s TV star who has not been investigated by operation YewTree, and we wonder why Intel is talking about it at all.

Perhaps it might because Intel is attempting to reassure customers that there’s a roadmap stretching out beyond the Knight’s Landing product and the 14nm node.

Intel’s Omni-Path scaling architecture debuts next year. Omni-Path is Intel’s next-generation networking interconnect that handles up to 100Gbps of bandwidth and uses silicon photonics technology for signalling. The new standard offers up to 48 ports per switch compared to 36 ports on other top-end standards, and is designed to lower the cost of huge build-outs by reducing the total number of switches. The long  term goal is to reduce latency and allow for effective scaling as the industry pushes forwards towards exascale. Bring back Pat Gelsinger!

Future versions of the core will likely expand both the onboard memory pool (16GB is expected for Knight’s Landing; Knight’s Hill could pack 32GB or more), add additional bandwidth, and likely increase the interconnect performance between the CPU and the associated MIC.

According to Extreme Tech  Intel might push its AVX standard up as high as 1024-bit registers, if the HPC crowd wants it. Adding wider registers is a simple way to boost performance The current AVX specification allows for extensions of up to 1024 bits in length, however, so Intel could do this. [Does anybody apart from Extreme Tech believe this Intel crap any more? Ed.]